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1 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c S2009 ? 1.6 gbps quad serial backplane device device specification mac (asic) S2009 quad gigabit ethernet interface mac (asic) mac (asic) mac (asic) to serial backplane s2204 ge interface serial bp driver figure 1. typical quad gigabit ethernet application features ? cmos technology ? broad operating rate range (1.3 - 1.6 gbps) - 1.6 gbps - 1/2 rate operation ? quad transmitter with phase-lock loop (pll) clock synthesis from low speed reference ? quad receiver pll provides clock and data recovery ? internally series terminated ttl outputs ? on-chip 8b/10b line encoding and decoding for four separate parallel 8-bit channels ? 32-bit parallel ttl interface with internal series terminated outputs ? low-jitter serial pecl interface ? individual local loopback control ? jtag 1149.1 boundary scan on low speed i/o signals ? interfaces with coax, twinax, or fiber optics ? single +3.3 v supply, 2.65 w power dissipation ? compact 23 mm x 23 mm 208 pin tbga package applications ? ethernet backbones ? workstation ? frame buffer ? switched networks ? data broadcast environments ? proprietary extended backplanes general description the S2009 facilitates high-speed serial transmission of data in a variety of applications including gigabit ethernet, serial backplanes, and proprietary point to point links. the chip provides four separate trans- ceivers which can be operated individually or locked together for an aggregate data capacity of >5 gbps. each bi-directional channel provides 8b/10b coding/ decoding, parallel-to-serial and serial-to-parallel con- version, clock generation/recovery, and framing. the on-chip transmit pll synthesizes the high-speed clock from a low-speed reference. the on-chip quad receive pll is used for clock recovery and data re- timing on the four independent data inputs. the transmitter and receiver each support differential pecl-compatible i/o for copper or fiber optic com- ponent interfaces with excellent signal integrity. lo- cal loopback mode allows for system diagnostics. the chip requires a +3.3 v power supply and dissi- pates 2.65 watts. figure 1 shows the S2009 and s2204 in a gigabit ethernet application. figure 2 combines the S2009 with a crosspoint switch to demonstrate a serial backplane application. figure 3 is the input/output diagram. figures 4 and 5 show the transmit and receive block diagrams, respectively.
2 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c figure 2. typical serial backplane application mac (asic) S2009 atm gigabit ethernet etc. mac (asic) mac (asic) mac (asic) crosspoint switch s2016 s2025 mac (asic) S2009 atm gigabit ethernet etc. mac (asic) mac (asic) mac (asic) mac (asic) S2009 atm gigabit ethernet etc. mac (asic) mac (asic) mac (asic) mac (asic) S2009 atm gigabit ethernet etc. mac (asic) mac (asic) mac (asic) backplane signal group
3 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c figure 3. S2009 input/output diagram refclk rate reset_n tclko sync tclko2 txap/n txbp/n txcp/n txdp/n rxap/n rxbp/n rxcp/n rxdp/n dina[0:7] dna, kgena 10 dinb[0:7] dnb, kgenb 10 dinc[0:7] dnc, kgenc 10 dind[0:7] dnd, kgend 10 tclka sqla_n tclkb sqlb_n tclkc sqlc_n tclkd sqld_n 10 rca p/n 10 rcb p/n 10 rcc p/n 10 rcd p/n douta[0:7] eofa, kflaga doutb[0:7] eofb, kflagb doutc[0:7] eofc, kflagc doutd[0:7] eofd, kflagd ch_lock erra lola lolb lolc lold errb errc errd cmode lpena lpenb lpenc lpend trs tms tck tdi tdo
4 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c figure 4. transmitter block diagram 8b/10b encode 8 10 sync dna kgena dina[0:7] 8 dnb kgenb dnc kgenc dnd kgend reset_n shift reg 8b/10b encode 8 10 dinb[0:7] 8 shift reg tclkb 8b/10b encode 8 10 dinc[0:7] 8 shift reg tclkc 8b/10b encode 8 10 dind[0:7] 8 shift reg tclkd din pll 20x rate refclk refclk tclko tclko2 fifo (input) fifo (input) fifo (input) fifo (input) tclka ch_lock 0 1 0 1 0 1 0 1 txap txan txabp txbp txbn txbbp txcp txcn txcbp txdp sqld_n txdn txdbp divide by 2 sqlc_n sqlb_n sqla_n
5 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c figure 5. receiver block diagram dout cru serial- parallel dout cru serial- parallel eofa kflaga erra douta[0:7] rxap rxan lpena rxbp rxbn lpenb eofb kflagb errb doutb[0:7] q fifo (output) dout cru serial- parallel eofd kflagd errd doutd[0:7] rxdp rxdn lpend reset_n dout cru serial- parallel eofc kflagc errc doutc[0:7] rxcp rxcn lpenc txdbp txcbp txbbp txabp refclk 8 8b/10b decode 8 8 8 8 rcap/n lola rcbp/n rccp/n rcdp/n cmode rate fifo (output) fifo (output) fifo (output) ch_lock 8 8 8 10 10 10 10 lolb lolc lold framing data stretching timing 8b/10b decode framing data stretching timing 8b/10b decode framing data stretching timing 8b/10b decode framing data stretching timing
6 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c table 1. input modes k c o l _ h cn o i t a r e p o 0 k c o l c o t d e s u x k l c t . e d o m x k l c t . e d o m t n e d n e p e d n i ) . w e k s - e d e t y b r e v i e c e r o n ( . s l e n n a h c l l a r o f s o f i f o t n i a t a d 1 o t d e s u a k l c t . e d o m a k l c t . e d o m k c o l l e n n a h c w e k s - e d e t y b r e v i e c e r ( . s l e n n a h c l l a r o f s o f i f o t n i a t a d k c o l c ) . e v i t c a 1. note that internal synchronization of fifos is performed upon de-assertion of reset_n or when the synchronization pattern is generated (sync = 1 dnx = 1). transmitter description the transmitter section of the S2009 contains a single pll which is used to generate the serial rate transmit clock for all transmitters. four channels are provided with a variety of options regarding input clocking and loopback. the transmitters can operate in the range of 1.3 to 1.6 ghz, 20 times the refer- ence clock frequency. data input the S2009 has been designed to simplify the paral- lel interface data transfer and provides the utmost in flexibility regarding clocking of parallel data. the S2009 incorporates a unique fifo structure on both the parallel inputs and the parallel outputs which en- ables the user to provide a clean reference source for the pll and to accept a separate external clock which is used exclusively to reliably clock data into the device. data is input to each channel of the S2009 nominally as 10-bit parallel data. this consists of eight data bits of user data, kgen, and dn. an input fifo and a clock input, tclkx, are provided for each channel of the S2009. the device can operate in two different modes. in channel lock mode, all four bytes of input data are clocked into their respective fifos using the tclka clock. in independent mode, each byte of data is clocked into its fifo with the tclkx pro- vided with each byte. table 1 provides a summary of the input modes for the S2009. operation in the tclk mode makes it easier for users to meet the relatively narrow setup and hold time win- dow required by the parallel 10-bit interface. the tclkx signal is used to clock the data into an internal holding register and the S2009 synchronizes its inter- nal data flow to insure stable operation. however, re- gardless of the clock mode, refclk is always the vco reference clock. this facilitates the provision of a clean reference clock resulting in minimum jitter on the serial output. the tclkx must be frequency locked to refclk, but may have an arbitrary phase relation- ship. adjustment of internal timing of the S2009 is per- formed during reset. once synchronized, the user must insure that the timing of the tclkx signal does not change by more than 3 ns relative to the refclk.
7 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c figure 6. dinx data clocking with tclk figure 6 demonstrates the flexibility afforded by the S2009. a low jitter reference is provided directly to the S2009 at 1/20 the serial data rate. two system clock outputs are provided from the S2009 at both the par- allel word rate (tclko) and the parallel word rate divided by two (tclko2). these two outputs are de- rived from the pll and are provided to the upstream circuit as system clocks. the frequency of the tclko output is constant at the parallel word rate, 1/10 the serial data rate. the tclko2 frequency is constant at the parallel word rate divided by two, 1/20 the serial data rate. these clocks can be buffered as required without concern about added delay. there is no phase requirement between tclko or tclko2 and tclkx, which are provided back to the S2009, other than that the output clock that is chosen and tclkx remain within 3 ns of the phase relationship estab- lished at reset. refclk S2009 vco/20 tclkx dinx[0:7] ref oscillator mac asic tclko pll 1 1. a.x. widner and p.a. franaszek, "a byte-oriented dc bal- anced (0,4) 8b/10b transmission code," ibm research report rc9391, may 1982. half rate operation the S2009 supports full and 1/2 rate operation for all modes of operation. when rate is low, the S2009 serial data rate equals the vco frequency. when rate is high, the vco is divided by 2 before being provided to the chip. the half rate range for the serial data will be between 650 and 800 mhz. thus the S2009 can support serial backplane functions at both full and 1/2 the vco rate. see table 5. 8b/10b coding the S2009 provides 8b/10b line coding for each channel. the 8b/10b transmission code includes se- rial encoding and decoding rules, special characters, and error control. information is encoded, 8 bits at a time, into a 10-bit transmission character. the char- acters defined by this code ensure that enough tran- sitions are present in the serial bit stream to make clock recovery possible at the receiver. the encod- ing also greatly increases the likelihood of detecting any single or multiple errors that might occur during the transmission and reception of data 1 . the 8b/10b transmission code includes d-charac- ters, used for data transmission, and k-characters, used for control or protocol functions. each d-char- acter and k-character has a positive and a negative parity version. the parity of each codeword is se- lected by the encoder to control the running disparity of the data stream. k-character generation is con- trolled individually for each channel using the kgenx input. when kgen is asserted the data on the parallel input is mapped into the corresponding control character. the parity of the k-character is selected to minimize running disparity in the serial data stream. table 3 lists the k characters sup- ported by the S2009 and identifies the mapping of the din[7:0] bits to each character.
8 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c table 3. k character generation (dnx = 1 kgenx =1 sync = 0) k r e t c a r a h c ] 0 : 7 [ n i dn e g k + d r t n e r r u c- d r t n e r r u c s t n e m m o c j h g f i e d c b aj h g f i e d c b a 0 . 8 2 k 1 . 8 2 k 2 . 8 2 k 3 . 8 2 k 4 . 8 2 k 5 . 8 2 k 6 . 8 2 k 7 . 8 2 k 7 . 3 2 k 7 . 7 2 k 7 . 9 2 k 7 . 0 3 k 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 r e t c a r a h c c n y s in order to provide interface compatibility to non- amcc serial backplane transceivers, the S2009 can also generate a unique sync character consisting of 16 consecutive k28.5 characters. this event is initi- ated by the simultaneous assertion of sync and dn. the sync character may start with either a positive or negative parity k28.5. (depending on the current running disparity.) the parity of the second and third k28.5 are inverse with respect to a valid 8b/10b sequence. parity of the remaining k28.5 are 8b/10b compliant. thus the parity of the k28.5 pat- tern consists of + + - - + - + - + - + - + - + - or - - + + - + - + - + - + - + - +. when operating in the channel lock mode, the kgenx and dnx inputs must be driven for each channel. the sync input is common to all four channels. table 2 identifies the S2009 transmit con- trol signals. c n y sx n e g kx n dt u p t u o 9 0 0 2 s 000 . a t a d l e l l a r a p d e d o c n e 001 . r e t c a r a h c 5 . 8 2 k 011 d n a 3 e l b a t y b d e n i f e d s a r e t c a r a h c k . ] 0 : 7 [ n i d 1x1 d e t a r e n e g r e t c a r a h c c n y s d r o w 6 1 l a i c e p s . o f i f t i m s n a r t e h t s t e s e r d n a the special sync generation commences on the first cycle in which sync and dn=1 and continues for 16 cycles. during this period, the sync, kgen, and dn inputs are ignored (assertion of dn and sync during this period will not prolong or re-initialize the special sync character generation). frequency synthesizer (pll) the S2009 synthesizes a serial transmit clock from the reference signal. upon startup, the S2009 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock in- puts. reliable locking of the transmit pll is assured, but a lock-detect output is not provided. table 2. transmitter control signals note: 010, 100, and 110 are reserved states.
9 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c table 4. data to 8b/10b alphabetic representation e t y b a t a d ] 9 : 0 [ t u o d r o ] 9 : 0 [ n i d 0123456789 b 0 1 / b 8 n o i t a t n e s e r p e r c i r e m u n a h p l a abcdei fghj table 5. operating rates reference clock input the reference clock input must be supplied with a low-jitter clock source. all reference clocks in a sys- tem must be within 100 ppm of each other to en- sure that the clock recovery units can lock to the serial data. the frequency of the reference clock is 1/20 the se- rial data rate. the frequency of the parallel word rate output, tclko, is constant at 1/10 the serial data rate, while the tclko2 output is constant at 1/20 the serial data rate. see table 5. serial data outputs the S2009 provides lvpecl level serial outputs. the serial ouputs do not require output pulldown re- sistors. outputs are designed to perform optimally when ac-coupled. when operating in the channel lock mode, the user must insure that the path length of the four high speed serial data signals are matched to within 50 bit times of delay. failure to meet this requirement may result in bit errors in the received data or in byte misalign- ment. in addition to path length induced timing skew, the S2009 can tolerate up to 3 ns of phase drift be- tween channels after deskewing the outputs. test functions the S2009 can be configured for factory test to aid in functional testing of the device. when in the test mode, the internal transmit and receive voltage con- trolled oscillator (vco) is bypassed and the refer- ence clock substituted. this allows full functional testing of the digital portion of the chip or bypassing the internal synthesized clock with an external clock source. (see other operating modes section.) transmit fifo initialization the transmit fifo must be initialized after stable delivery of data and tclk to the parallel interface, and before entering the normal operational state of the circuit. fifo initialization is performed upon the de-assertion of the reset_n signal. the transmit fifo is also reset when the special synchronization pattern (sync=1, dn=1) is generated. tclko and tclko2 will operate normally regardless of the state of reset_n. k l c f e r y c n e u q e r f l a i r e s e t a r t u p t u o o k l c t y c n e u q e r f 2 o k l c t y c n e u q e r f 0 2 / r d sz h g 6 . 1 - 3 . 10 1 / r d s0 2 / r d s note: sdr = serial data rate.
10 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c receiver description each receiver channel is designed to implement a serial backplane receiver function through the physi- cal layer. a block diagram showing the basic func- tion is provided in figure 5. whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. after acquiring bit synchronization, the S2009 searches the serial bit stream for the occur- rence of a k28.5 character on which to perform word synchronization. once synchronization on both bit and word boundaries is achieved, the receiver pro- vides the decoded data on its parallel outputs. the S2009 provides the capability to operate with all four channels locked together (channel lock mode). channel lock process and status reporting is de- scribed below. data input a differential input receiver is provided for each chan- nel of the S2009. each channel has a loopback mode in which the serial data from the transmitter replaces external serial data. the loopback function for each channel is enabled by its respective lpen input. the high speed serial inputs to the S2009 are internally biased to v dd -1.3 v. all that is required externally is ac-coupling and line-to-line differential termination. clock recovery function clock recovery is performed on the input data stream for each channel of the S2009. the receiver pll has been optimized for the anticipated needs of serial backplane systems. a simple state machine in the clock recovery macro decides whether to acquire lock from the serial data input or from the reference clock. the decision is based upon the frequency and run length of the serial data inputs. if at any time the frequency or run length checks are violated, the state machine forces the receive pll to lock to the reference clock. this allows the pll to maintain the correct frequency in the absence of data. the lock to reference frequency criteria insure that the S2009 will respond to variations in the serial data input frequency (compared to the reference frequency). the new lock state is dependent upon the current lock state, as shown in table 6. the run length criteria ensure that the S2009 will re- spond appropriately and quickly to a loss of signal. the run length checker flags a condition of consecutive ones or zeros across 12 parallel words. thus 119 or less consecutive ones or zeros does not cause signal loss, 160 or more causes signal loss, and 120 through 159 may or may not, depending on how the data aligns across the four clock byte boundaries. when the run length checker criterion is exceeded, loss of sync will report independently on each channel until the consecutive ones or zeros stream sees a change in polarity and the receive pll has locked to the serial data input. if both the off-frequency detect circuitry test and the run length test are satisfied, the cru will attempt to lock to the incoming data. when lock is achieved, loss of lock is removed on the errx, eofx, and kflagx status lines. lolx will report a logic 0 when lock is achieved (lolx is an asynchronous, unfiltered signal). the unfiltered lolx pins will have a tendency to pulse high and low between pll lock and unlock. when the pll is trying to acquire lock, it tends to drift in and out of lock. this is due to the pll always trying to lock to data until it finally achieves lock to the receive data stream, therefore, during this situation you can have rapid high and low changes on the lolx outputs. when the receive pll locks to data, the lolx signal is stable. it is possible for the run length test to be satis- fied due to noise on the inputs, even if no signal is present. in this case the lock detect status may periodi- cally assert as the receive pll frequency approaches that of the refclk. in any transfer of pll control from the serial data to the reference clock, the rcxp/n outputs remain phase continuous and glitch free, assuring the integrity of downstream clocking. k c o l t n e r r u c e t a t se t a t s e t a t s e t a t se t a t s y c n e u q e r f l l p ) k l c f e r . s v () k l c f e r . s v ( ) k l c f e r . s v ( ) k l c f e r . s v () k l c f e r . s v ( e t a t s k c o l w e n d e k c o l m p p 8 8 4 d e k c o l n u d e k c o l n u m p p 4 4 2 d e k c o l n u table 6. lock to reference frequency criteria
11 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c when operating in independent mode, pll loss of lock status for each channel is indicated by a continu- ous 1-0-1 on its respective err, eof, and kflag outputs. lolx will report a logic 1 asynchronously when loss of lock occurs. when operating in the channel lock m ode, pll locking of all four channels must be accomplished before byte-skewing is achieved and channel lock detected status can be indicated on the err, eof, kflag, and lol outputs. reference clock input a single reference clock, which serves both transmit- ter and receiver, must be provided from a low jitter clock source. the frequency of the received data stream (divided-by-20) must be within 100 ppm of the reference clock to insure reliable locking of the receiver pll. serial-to-parallel conversion once bit synchronization has been attained by the S2009 cru, the S2009 must synchronize to the 10- bit word boundary. word synchronization in the S2009 is accomplished by detecting and aligning to the 8b/10b k28.5 codeword. the S2009 will detect and byte-align to either polarity of the k28.5. each channel of the S2009 will detect and align to a k28.5 anywhere in the data stream. two modes of opera- tion are supported: normal mode, in which the chan- nels operate independently and channel lock mode, in which the channels are locked together to form a virtual 32-bit interface. for channel lock operation, the S2009 must provide an additional level of synchronization to insure that differences in delay encountered by the four channels do not result in parallel output data from each channel leading or lagging by one parallel clock cycle. in channel lock mode, assertion of dna results in the k28.5 being transmitted simultaneously on all four channels. each receiver provides a fifo buffer and adjusts the delay through this buffer to ensure that the first data following the k28.5 is output simultaneously from the receiver on the parallel interface. table 7 details the function of the eof, kflag, err, and lol pins in status reporting. for channel lock opera- tion, a single output clock, rca p/n, is provided syn- chronous with the data. the other rcx p/n clocks will be frequency locked, but will have an arbitrary phase relationship with the data. channel lock mode synchronization incidental errors occurring in the received data can transform a normal data character into a k28.5 char- acter. to prevent this occurrence from making the channel locking process unnecessarily vulnerable to bit errors, the S2009 implements a channel lock state machine for each channel with linkage between channels to move to the final deskewed state. the channel lock state diagram is shown in figure 7. the S2009 powers up in the no sync state. when in the no sync state, each channel of the S2009 is actively searching the received data stream for the occurrence of a k28.5 and will align its de- multiplexer to the character when detected, and will enter the acquiring sync state. k28.5 will be reported on each channel as 0-1-1 (err-eof-kflag). when four or more con- secutive k28.5 characters are received on a given chan- nel, the channel will enter the re-sync state as shown in figure 7. re-sync state status will be reported as 1-1-1 until the S2009 deskewing circuitry has aligned the data output from each channel such that the first valid non-errored codeword (or data character) other than a k28.5 for each channel is output simultaneously 1 . the device will move to the in sync state and indicate chan- nel lock status by each channel as a 0-1-0. see figure 8. note that re-sync is reported independently by each channel regardless of the state of the other channels. however, in sync can only be reported when all four channels are in the in sync state and detect a valid data character within the deskew window 2 . the in sync state is reported simultaneously for each channel as 0-1-0. once the S2009 has entered the in sync state, it will report status but will not alter the relative skew of the output fifos. the S2009 will exit the in sync state and move to the no sync state if one of the four crus reports a loss of lock, if the 8b/10b decoder observes five consecutive decoding errors, or if the decoder error rate >50% in a block of 16 codewords. the error rate of greater than 50% in a block of 16 and five or more se- quential decoding errors is calculated on a per k28.5 basis. the error counter resets whenever a k28.5 char- acter is received or an unlock condition occurs. the device can also be put in the no sync state by setting tclkd=low for at least 16 clocks, or by asserting reset_n low. 1. note, if the S2009 does not have to delay any of the channels for word alignment, re-sync reporting (1-1-1) will not be seen and channel lock status will be reported simultaneously on the four channels as 0-1-0. 2. note when cmode = 0, if the deskew window to channel lock is exceeded, indeterminate status will be reported.
12 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c figure 7. channel lock state machine re-sync no sync in sync all four channels in re-sync with valid data within deskew window errored codeword or cru loss of lock or five sequential decoding errors or decoding error rate >50% (block 16) or valid data not within deskew window or tclkd = low for at least 16 clocks reset_n acquiring sync one k28.5 detected 3 4 k28.5 detected errored codeword or <4 k28.5 or cru loss of lock or five sequential decoding errors or decoding error rate >50% (block 16) or tclkd = low for at least 16 clocks tclkd = low for at least 16 clocks or cru loss of lock or five sequential decoding errors or decoding error rate >50% (block 16) note: errored codeword means codeword violation or parity error. tclkd is used to reset the channel lock state machine and initialize the fifos in the receive data path. assertion of tclkd low does not interrupt the transmit data path. when not in channel lock mode, the linkage between the four state machines is broken and each channel oper- ates independently. loss of channel lock will be reported as indicated in table 7 by a 1-0-1 on the err, eof, and kflag sig- nals, respectively. this is during the no sync state. the status lines will reflect the status of the individual channels and the device will respond to appropriate channel locking sequences and deskew as necessary. persistence of 1- 0-1 status on any channel or a logic 1 on lolx is indica- tive of cru lock failure, most likely resulting from loss of receiver input signal. the device will then respond to the channel locking sequence. when operating in the channel lock mode, the tclkb input must be tied low.
13 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c figure 8. channel lock synchronization timing (internal) resync a (internal) resync b (internal) resync c (internal) resync d (internal) deskewed resync a (internal) deskewed resync b (internal) deskewed resync c (internal) deskewed resync d fifo deskewing .... .... .... .... .... .... .... .... fifo deskewed (internal) channel lock a,b,c,d .... errx eofx kflagx rx data out .... .... .... .... bc (k28.5) valid data bc (k28.5) bc (k28.5) bc (k28.5) bc valid data bc bc bc 0 1 0 0 1 1 0 1 0 *notes 1, 2 1. the first three k28.5s will be reported as k28.5 (011), subsequent k28.5 will be reported as re-sync or channel lock d etected. see table 7. 2. re-sync(s) (111 status) may be seen on the parallel outputs during re-sync due to deskewing function.
14 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c r r ef o eg a l f kn o i t p i r c s e dk n a r 00 0 . d e t c e t e d n e e b s a h r e t c a r a h c a t a d d i l a v a t a h t s e t a c i d n i . r e t c a r a h c l a m r o n 7 00 1 s a h 5 . 8 2 k n a h t r e h t o r e t c a r a h c k a t a h t s e t a c i d n i . ) 5 . 8 2 k t o n ( r e t c a r a h c k . d e t c e t e d n e e b 7 01 0 d e t c e t e d k c o l l e n n a h c 1 , x f o e , x r r e e h t n o d r o w l e l l a r a p e n o r o f s t r e s s a . " c n y s - e r " e h t d e i f i t n e d i e v a h s l e n n a h c r u o f l l a t a h t s l a n g i s x g a l f k d n a e h t , e t a t s " c n y s n i " e h t n i n e h w . w o d n i w w e k s e d e t y b e h t n i h t i w e c n e u q e s . s o f i f t u p t u o e h t w e k s e d - e r t o n l l i w t u b , s u t a t s t r o p e r o t e u n i t n o c l l i w 9 0 0 2 s 2 01 1 n e e b s a h y t i r a p y r a r t i b r a f o r e t c a r a h c 5 . 8 2 k a t a h t s e t a c i d n i . - 5 . 8 2 k r o + 5 . 8 2 k . d e t c e t e d 5 10 0 x . x d d i l a v y n a o t g n i d n o p s e r r o c t o n d r o w a t a h t s e t a c i d n i . n o i t a l o i v d r o w e d o c . d e v i e c e r n e e b s a h g n i p p a m x . x k r o 4 10 1 . c n y s f o s s o l ) 0 = k c o l _ h c ( e d o m t n e d n e p e d n i t i b u r c f o s s o l t a h t e t a c i d n i o t t r e s s a l l i w s u t a t s s i h t , e d o m t n e d n e p e d n i n i , x f o e , x r r e n o g n i t r o p e r l a u d i v i d n i . l e n n a h c c i f i c e p s a n o d e r u c c o s a h k c o l g n i t r o p e r s i h t . k c o l t i b t s o l s a h u r c s ' l e n n a h c h c i h w e t a c i d n i l l i w x g a l f k d n a o s l a l l i w " c n y s f o s s o l " . a t a d o t d e k c o l s a h u r c s t i l i t n u d e t r e s s a n i a m e r l l i w . d e d e e c x e s i n o i r e t i r c r e k c e h c h t g n e l n u r e h t n e h w t r e s s a ) 1 = k c o l _ h c ( e d o m k c o l l e n n a h c o t d r o w l e l l a r a p e n o t s a e l t a r o f t r e s s a l l i w s u t a t s s i h t , e d o m k c o l l e n n a h c n i s t l u s e r h c i h w ) s l e n n a h c r o ( l e n n a h c a n o d e r u c c o s a h n o i t i d n o c a t a h t e t a c i d n i l l a r o t i n o m t s u m r e s u e h t , d e k c o l l e n n a h c n e h w , e t o n . k c o l l e n n a h c f o s s o l n i n e e b s a h k n i l k c o l l e n n a h c e h t n e h w w o n k o t g n i t r o p e r s u t a t s ' s l e n n a h c r u o f o t e u n i t n o c l l i w s l e n n a h c d e r o r r e - n o n e h t . s l e n n a h c r u o f e h t n e e w t e b n e k o r b l e n n a h c a r o f d e t r o p e r e b o s l a l l i w s u t a t s " c n y s f o s s o l " . s u t a t s l a m r o n t r o p e r t r e s s a l l i w s u t a t s s i h t h c i h w n i e s a c r e h t o n a . a t a d o t d e k c o l s a h u r c s t i l i t n u . d e d e e c x e s i n o i r e t i r c r e k c e h c h t g n e l n u r e h t n e h w s i 1 11 0 . d e v r e s b o n e e b s a h r o r r e y t i r a p s i d g n i n n u r a t a h t s e t a c i d n i . r o r r e y t i r a p 6 11 1 c n y s - e r 1 r e h t o ) r e t c a r a h c a t a d r o ( d r o w e d o c d e r o r r e - n o n d i l a v + 4 x 5 . 8 2 k ( , t n e m n g i l a d r o w r o f d e y a l e d e b o t e v a h ) s ( l e n n a h c y n a f i . ) 5 . 8 2 k a n a h t y a l e d o t g n i v a h ) s ( l e n n a h c e s e h t n o r u c c o n a c ) s u t a t s 1 1 1 ( " s c n y s - e r " e l p i t l u m d e m r o f r e p s i ) g n i w e k s e d ( n o i t c n u f s i h t . t n e m n g i l a d r o w r e p o r p r o f s e v l e s m e h t r o f s l e n n a h c e h t f o y n a y a l e d o t e v a h t o n s e o d 9 0 0 2 s e h t f i . 9 0 0 2 s e h t n i h t i w s u t a t s k c o l l e n n a h c d n a n e e s e b t o n l l i w g n i t r o p e r " c n y s - e r " , t n e m n g i l a d r o w g n i t r o p e r " c n y s - e r " . s l e n n a h c r u o f l l a n o y l s u o e n a t l u m i s d e t r o p e r e b l l i w d i l a v a y b d e w o l l o f s r e t c a r a h c 5 . 8 2 k e v i t u c e s n o c e r o m r o r u o f t a h t s e t a c i d n i n e e b s a h 5 . 8 2 k a n a h t r e h t o ) r e t c a r a h c a t a d r o ( d r o w e d o c d e r o r r e - n o n r u o f l l a d n a y l t n e d n e p e d n i n o i t i d n o c s i h t s t r o p e r l e n n a h c h c a e . d e v i e c e r e r o f e b e m i t w e k s e d e t y b d e w o l l a e h t n i h t i w c n y s - e r e h t y f i t n e d i t s u m s l e n n a h c d e t c e t e d k c o l l e n n a h c h t i w d e t a c i d n i e b d n a d e v e i h c a e b n a c k c o l l e n n a h c . ) e v o b a e e s ( 3 l o ln o i t p i r c s e d 0. a t a d o t d e k c o l s i u r c e h t t a h t s e t a c i d n i 1 u r c e h t n e h w t r e s s a e d l l i w g n i t r o p e r s i h t . k c o l t i b t s o l s a h u r c e h t t a h t s e t a c i d n i . a t a d o t d e k c o l s a h table 7. error and status reporting, channel lock and independent mode note: lol is an asynchronous, unfiltered signal. 1. this status reporting is not available in independent mode (ch_lock = 0).
15 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c channel locking/re-locking procedure the channel locking/relocking procedures are sum- marized below. following these procedures will in- sure proper channel lock operation of the device. when powered up, the S2009 will lock to the re- ceived data within approximately 2500 bit times. the cru must report lock for approximately 32,000 refclk periods (320 m s) before channel locking is enabled. 1. ensure that the S2009 is in the no sync state. this can be accomplished by resetting the device (reset_n low) or by asserting tclkd low for at least 16 clocks. 2. the transmitter portion of another S2009 device initiates the appropriate synchronization se- quence. four or more k28.5 characters or the 16 word sync sequence followed by a valid non- errored codeword (or data character) other than a k28.5 can be used to de-skew the dout fifos. in the transmitter, the 16 word sync character can be generated by asserting sync=1 and dn[a:d]=1. see the transmit portion of the speci- fication for a complete description. 3. wait for channel lock detected as defined by table 7. while in the in sync state, the S2009 will enter the no sync state if: any cru loses lock, if five or more consecutive decoder errors are received, if the decoder error rate exceeds 50% in a block of 16 bytes, if reset_n is asserted low, or if tclkd is asserted low for at least 16 clocks. note that if any cru has failed to lock to the incoming data, this will be reported by the appropriate channel as loss of sync and loss of lock (lolx) (see table 7). to reacquire sync after moving to the no sync state, repeat steps 2 and 3 above. 8b/10b decoding after serial to parallel conversion, the S2009 pro- vides 8b/10b decoding of the data. the received 10- bit code word is decoded to recover the original 8-bit data. the decoder reports either invalid code word errors or running disparity errors. error type is deter- mined by examining table 7. when more than one reportable condition occurs simultaneously, reporting is in accordance with the rank assigned by table 7. data output data is output on the dout[0:7] outputs. k-characters are flagged using the kflag signal. the eof (with kflag) is used to indicate the reception of a valid k28.5 character. invalid codewords and decoding er- rors are indicated on the err output. kflag, eof, and err are buffered with the data in the fifo to insure that all outputs are synchronized at the S2009 outputs. errors are reported independently for each channel in both channel lock mode and indepen- dent mode operation. the S2009 ttl outputs are optimized to drive 65 w line impedances. internal source matching provides good performance on unterminated lines of reason- able length. parallel output clock rate two output clock modes are supported, as shown in table 8. when cmode is high, a complementary ttl clock at the data rate is provided on the rcxp/n outputs. data should be clocked on the rising edge of rcxp. when cmode is low, a complementary ttl clock at 1/2 the data rate is provided. data should be latched on the rising edge of rcxp and the rising edge of rcxn. the S2009 follows the gigabit ethernet standard which requires that the parallel clock output rate be at half the word rate. in addition, the phase of the rcxp/n clock must be adjusted such that the k28.5 appears on the rising edge of the rcxp signal. to insure compatibility with the gigabit ethernet stan- dard, the S2009 will buffer data such that this re- quirement is met. this concept is referred to as data stretching. in gigabit ethernet applications, multiple consecu- tive k28.5 characters should not be generated. how- ever, for serial backplane applications this can occur. the S2009 must be able to operate properly when multiple k28.5 characters are received. when cmode is low, the S2009 guarantees that the last k28.5 character before a non-k28.5 character will always line up with the rising edge of rcxp. be- cause of this, the last data character or codeword (including k28.5) prior to a sequence of one or more k28.5 characters may be either duplicated or lost.
16 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c e d o me d o m cq e r f n / p x c r e d o m k c o l c f l a h00 2 / o c v e d o m k c o l c l l u f10 1 / o c v table 8. output clock mode k c o l _ h ce c r u o s k c o l c t u p n ie c r u o s k c o l c t u p t u o 0x k l c t) x u r c m o r f d e v i r e d ( x c r 1a k l c t) a u r c m o r f d e v i r e d ( a c r table 8a. S2009 data clocking
17 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c figure 9. S2009 diagnostic loopback operation cru csu other operating modes operating frequency range the S2009 is designed to operate at serial baud rates of 1.3 to 1.6 ghz (1.04 C 1.28 gbps user data rate). loopback mode when loopback mode is enabled, the serial data from the transmitter is provided to the serial input of the receiver, as shown in figure 9. this provides the ability to perform system diagnostics and off-line testing of the interface to verify the integrity of the serial channel. loopback mode is enabled indepen- dently for each channel using its respective loopback enable input (lpenx). when squelch is enabled, the transmitter output driver is powered down. the serial outputs (txp and txn) will be held at a logic high state due to source followers, which in turn makes the differential state, txp minus txn, indeterminate. squelch is enabled independently for each channel using its respective squelch input (sqlx_n). test modes the S2009 has a testability input to aid in functional testing of the device. the test mode is entered when ch_lock is high and tclkb is high. thus users must take care to insure that tclkb is held low when operating in channel lock mode. notes: 1. serial output data remains active during loopback operation to enable other system tests to be performed. 2. serial output data will become inactive during squelch operation jtag testing the jtag implementation for the S2009 is compli- ant with the ieee1149.1 requirements. jtag is used to test the connectivity of the pins on the chip. the test access port (tap) provides access to the test logic of the chip. when test reset (trs) is asserted the tap is initialized. tap is a state machine that is controlled by test mode select (tms). the test in- struction and data are loaded through test data in (tdi) on the rising edge of test clock (tck). when tms is high, the test instruction is loaded into the instruction register. when tms is low, the test data is loaded into the data register. test data out (tdo) changes on the falling edge of tck. all input pins, including clocks, that have boundary scan are ob- serve only. they can be sampled in either normal operational or test mode. all output pins that have boundary scan, are observe and control. they can be sampled as they are driven out of the chip in normal operational mode, and they can be driven out of the chip in test mode using the extest instruction. since jtag testing operates only on digital signals there are some pins with analog signals that jtag does not cover. the jtag implementation has the three required instruction, bypass, extest, and sample/preload. jtag instruction description: the bypass register contains a single shift-register stage and is used to provide a minimum-length serial path between the tdi and tdo pins of a component when no test operation of that component is required. this allows more rapid movement of test data to and from other com- ponents on a board that are required to perform test op- erations. the extest instruction allows testing of off-chip circuitry and board level interconnections. data would typically be loaded onto the latched parallel outputs of boundary-scan shift-register stages using the sample/preload in- struction prior to selection of the extest instruction. the sample/preload instruction allows a snapshot of the normal operation of the component to be taken and examined. it also allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift register prior to selection of the other boundary-scan test instruc- tions. the idcode instruction allows selection of the de- vice identification register to be connected for serial access between test data input (tdi) and test data output (tdo). when the idcode instruction of the device is selected, all test data registers perform their system function.
18 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c the following table provides a list of the pins that are jtag tested. each port has a boundary scan register (bsr), unless otherwise noted. the following features are described: the jtag mode of each register (input, output2, or internal (refers to an internal package pin)), the direction of the port if it has a boundary scan register (in or out), and the position of this register on the scan chain. 9 0 0 2 s e m a n n i p n a c s _ e r o c e m a n t r o p g a t j e d o m g n i t u o r t u o n i c n y sc n y st u p n i0- e d o m ce d o m ct u p n i1- k c o l _ h ck c o l _ n a h ct u p n i2- d n e p ld n e p lt u p n i3- c n e p lc n e p lt u p n i4- b n e p lb n e p lt u p n i5- a n e p la n e p lt u p n i6- l a n r e t n i7- l a n r e t n i8- l a n r e t n i9- n _ t e s e rt e s e rt u p n i0 1- k l c f e rk l c f e rt u p n i1 1- o k l c t f u b _ k l c _ t i m s n a r t t u o _ 2 t u p t u o-2 1 d n dd n dt u p n i3 1- d n e g kd n e g kt u p n i4 1- 7 d n i d) 7 ( d _ n i a t a d tt u p n i5 1- 6 d n i d) 6 ( d _ n i a t a d tt u p n i6 1- 5 d n i d) 5 ( d _ n i a t a d tt u p n i7 1- 4 d n i d) 4 ( d _ n i a t a d tt u p n i8 1- 3 d n i d) 3 ( d _ n i a t a d tt u p n i9 1- 2 d n i d) 2 ( d _ n i a t a d tt u p n i0 2- 1 d n i d) 1 ( d _ n i a t a d tt u p n i1 2- 0 d n i d) 0 ( d _ n i a t a d tt u p n i2 2- d k l c td k l c tt u p n i3 2- c n dc n dt u p n i4 2- c n e g kc n e g kt u p n i5 2- 7 c n i d) 7 ( c _ n i a t a d tt u p n i6 2- 6 c n i d) 6 ( c _ n i a t a d tt u p n i7 2- 5 c n i d) 5 ( c _ n i a t a d tt u p n i8 2- 4 c n i d) 4 ( c _ n i a t a d tt u p n i9 2- 3 c n i d) 3 ( c _ n i a t a d tt u p n i0 3- 2 c n i d) 2 ( c _ n i a t a d tt u p n i1 3- 1 c n i d) 1 ( c _ n i a t a d tt u p n i2 3- 0 c n i d) 0 ( c _ n i a t a d tt u p n i3 3- c k l c tc k l c tt u p n i4 3- b n e g kb n e g kt u p n i5 3- b n db n dt u p n i6 3- 7 b n i d) 7 ( b _ n i a t a d tt u p n i7 3- 6 b n i d) 6 ( b _ n i a t a d tt u p n i8 3- 5 b n i d) 5 ( b _ n i a t a d tt u p n i9 3- table 9. jtag pin assignments 9 0 0 2 s e m a n n i p n a c s _ e r o c e m a n t r o p g a t j e d o m g n i t u o r t u o n i 4 b n i d) 4 ( b _ n i a t a d tt u p n i0 4- 3 b n i d) 3 ( b _ n i a t a d tt u p n i1 4- 2 b n i d) 2 ( b _ n i a t a d tt u p n i2 4- 1 b n i d) 1 ( b _ n i a t a d tt u p n i3 4- 0 b n i d) 0 ( b _ n i a t a d tt u p n i4 4- b k l c tb k l c tt u p n i5 4- a n da n dt u p n i6 4- a n e g ka n e g kt u p n i7 4- 7 a n i d) 7 ( a _ n i a t a d tt u p n i8 4- 6 a n i d) 6 ( a _ n i a t a d tt u p n i9 4- 5 a n i d) 5 ( a _ n i a t a d tt u p n i0 5- 4 a n i d) 4 ( a _ n i a t a d tt u p n i1 5- 3 a n i d) 3 ( a _ n i a t a d tt u p n i2 5- 2 a n i d) 2 ( a _ n i a t a d tt u p n i3 5- 1 a n i d) 1 ( a _ n i a t a d tt u p n i4 5- 0 a n i d) 0 ( a _ n i a t a d tt u p n i5 5- a k l c ta k l c tt u p n i6 5- p d c rp d c r2 t u p t u o-7 5 n d c rn d c r2 t u p t u o-8 5 7 d t u o d) 7 ( d _ t u o a t a d r2 t u p t u o-9 5 6 d t u o d) 6 ( d _ t u o a t a d r2 t u p t u o-0 6 5 d t u o d) 5 ( d _ t u o a t a d r2 t u p t u o-1 6 4 d t u o d) 4 ( d _ t u o a t a d r2 t u p t u o-2 6 3 d t u o d) 3 ( d _ t u o a t a d r2 t u p t u o-3 6 2 d t u o d) 2 ( d _ t u o a t a d r2 t u p t u o-4 6 1 d t u o d) 1 ( d _ t u o a t a d r2 t u p t u o-5 6 0 d t u o d) 0 ( d _ t u o a t a d r2 t u p t u o-6 6 d f o ed _ d f o e2 t u p t u o-7 6 d g a l f kd _ d g a l f k2 t u p t u o-8 6 d r r ed _ d r r e2 t u p t u o-9 6 p c c rp c c r2 t u p t u o-0 7 n c c rn c c r2 t u p t u o-1 7 7 c t u o d) 7 ( c _ t u o a t a d r2 t u p t u o-2 7 6 c t u o d) 6 ( c _ t u o a t a d r2 t u p t u o-3 7 5 c t u o d) 5 ( c _ t u o a t a d r2 t u p t u o-4 7 4 c t u o d) 4 ( c _ t u o a t a d r2 t u p t u o-5 7 3 c t u o d) 3 ( c _ t u o a t a d r2 t u p t u o-6 7 2 c t u o d) 2 ( c _ t u o a t a d r2 t u p t u o-7 7 1 c t u o d) 1 ( c _ t u o a t a d r2 t u p t u o-8 7 0 c t u o d) 0 ( c _ t u o a t a d r2 t u p t u o-9 7
19 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c table 9. jtag pin assignments (continued) 9 0 0 2 s e m a n n i p n a c s _ e r o c e m a n t r o p g a t j e d o m g n i t u o r t u o n i c r r ec _ d r r e2 t u p t u o-0 8 c f o ec _ d f o e2 t u p t u o-1 8 c g a l f kc _ g a l f k2 t u p t u o-2 8 p b c rp b c r2 t u p t u o-3 8 n b c rn b c r2 t u p t u o-4 8 b g a l f kb _ d g a l f k2 t u p t u o-5 8 7 b t u o d) 7 ( b _ t u o a t a d r2 t u p t u o-6 8 6 b t u o d) 6 ( b _ t u o a t a d r2 t u p t u o-7 8 5 b t u o d) 5 ( b _ t u o a t a d r2 t u p t u o-8 8 4 b t u o d) 4 ( b _ t u o a t a d r2 t u p t u o-9 8 3 b t u o d) 3 ( b _ t u o a t a d r2 t u p t u o-0 9 2 b t u o d) 2 ( b _ t u o a t a d r2 t u p t u o-1 9 1 b t u o d) 1 ( b _ t u o a t a d r2 t u p t u o-2 9 0 b t u o d) 0 ( b _ t u o a t a d r2 t u p t u o-3 9 b f o eb _ d f o e2 t u p t u o-4 9 b r r eb _ d r r e2 t u p t u o-5 9 p a c rp a c r2 t u p t u o-6 9 n a c rn a c r2 t u p t u o-7 9 a r r ea _ d r r e2 t u p t u o-8 9 7 a t u o d) 7 ( a _ t u o a t a d r2 t u p t u o-9 9 6 a t u o d) 6 ( a _ t u o a t a d r2 t u p t u o-0 0 1 5 a t u o d) 5 ( a _ t u o a t a d r2 t u p t u o-1 0 1 4 a t u o d) 4 ( a _ t u o a t a d r2 t u p t u o-2 0 1 3 a t u o d) 3 ( a _ t u o a t a d r2 t u p t u o-3 0 1 2 a t u o d) 2 ( a _ t u o a t a d r2 t u p t u o-4 0 1 1 a t u o d) 1 ( a _ t u o a t a d r2 t u p t u o-5 0 1 0 a t u o d) 0 ( a _ t u o a t a d r2 t u p t u o-6 0 1 a f o ea _ d f o e2 t u p t u o-7 0 1 a g a l f ka _ d g a l f k2 t u p t u o-8 0 1 l a n r e t n i-9 0 1 9 0 0 2 s e m a n n i p n a c s _ e r o c e m a n t r o p g a t j e d o m g n i t u o r t u o n i s n i p l o r t n o c g a t j ) r e t s i g e r n a c s y r a d n u o b a e v a h t o n o d t a h t s t r o p ( k c tk c t _ g a t j--- i d ti d t _ g a t j--- o d to d t _ g a t j--- s m ts m t _ g a t j--- s r ts r t _ g a t j--- d e t s e t g a t j t o n s n i p p a x t---- n a x t---- p b x t---- n b x t---- p c x t---- n c x t---- p d x t---- n d x t---- e t a r---- p a x r---- n a x r---- p b x r---- n b x r---- p c x r---- n c x r---- p d x r---- n d x r---- 2 o k l c t---- a l o l---- b l o l---- c l o l---- d l o l---- n _ a l q s---- n _ b l q s---- n _ c l q s---- n _ d l q s----
20 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 a n i d 6 a n i d 5 a n i d 4 a n i d 3 a n i d 2 a n i d 1 a n i d 0 a n i d l t ti 2 1 p 2 1 r 3 1 t 2 1 t 3 1 u 1 1 p 1 1 r 1 1 t d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . a l e n n a h c r o f a t a d t i m s n a r t ) . 1 e l b a t e e s ( . a k l c t f o e g d e g n i s i r e h t n o n i a n dl t ti 5 1 u] 7 : 0 [ a n i d n o t n e s e r p a t a d , w o l n e h w . a l e n n a h c r o f t o n _ a t a d l a i c e p s , h g i h n e h w . y l l a i r e s d e t t i m s n a r t d n a d e d o c n e b 0 1 / b 8 s i . 2 e l b a t n i d e t a c i d n i s a d e t a r e n e g e r a s e c n e u q e s r e t c a r a h c a n e g kl t ti 4 1 ue h t s e s u a c h g i h a n e g k . a l e n n a h c r o f n o i t a r e n e g r e t c a r a h c - k e l b a t e e s ( . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ a n i d n o a t a d ) . 2 a k l c tl t ti 2 1 us i l a n g i s s i h t , w o l s i k c o l _ h c n e h w . a k c o l c a t a d t i m s n a r t e h t o t n i a n d d n a , a n e g k , ] 7 : 0 [ a n i d n o a t a d k c o l c o t d e s u l l a o t n i a t a d e h t s k c o l c a k l c t , h g i h s i k c o l _ h c n e h w . 9 0 0 2 s . s o f i f t i m s n a r t r u o f 7 b n i d 6 b n i d 5 b n i d 4 b n i d 3 b n i d 2 b n i d 1 b n i d 0 b n i d l t ti 5 1 r 4 1 p 5 1 t 4 1 r 7 1 u 6 1 u 3 1 p 4 1 t n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . b l e n n a h c r o f a t a d t i m s n a r t ) . 1 e l b a t e e s ( . b k l c t r o a k l c t f o e g d e g n i s i r e h t n o b n dl t ti 6 1 r] 7 : 0 [ b n i d n o t n e s e r p a t a d , w o l n e h w . b l e n n a h c r o f t o n _ a t a d l a i c e p s , h g i h n e h w . y l l a i r e s d e t t i m s n a r t d n a d e d o c n e b 0 1 / b 8 s i . 2 e l b a t n i d e t a c i d n i s a d e t a r e n e g e r a s e c n e u q e s r e t c a r a h c b n e g kl t ti 6 1 te h t s e s u a c h g i h b n e g k . b l e n n a h c r o f n o i t a r e n e g r e t c a r a h c - k e l b a t e e s ( . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ b n i d n o a t a d ) . 2 b k l c tl t ti 3 1 rs i l a n g i s s i h t , w o l s i k c o l _ h c n e h w . b k c o l c a t a d t i m s n a r t e h t o t n i b n d d n a , b n e g k , ] 7 : 0 [ b n i d n o a t a d k c o l c o t d e s u . w o l d e i t e b t s u m b k l c t , h g i h = k c o l _ h c n e h w . 9 0 0 2 s 7 c n i d 6 c n i d 5 c n i d 4 c n i d 3 c n i d 2 c n i d 1 c n i d 0 c n i d l t ti 5 1 m 6 1 n 4 1 m 7 1 r 6 1 p 5 1 n 7 1 t 4 1 n n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . c l e n n a h c r o f a t a d t i m s n a r t ) . 1 e l b a t e e s ( . c k l c t r o a k l c t f o e g d e g n i s i r e h t n o table 10. transmitter input pin assignment and descriptions
21 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c table 10. transmitter signal input pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d c n dl t ti 7 1 n] 7 : 0 [ c n i d n o t n e s e r p a t a d , w o l n e h w . c l e n n a h c r o f t o n _ a t a d l a i c e p s , h g i h n e h w . y l l a i r e s d e t t i m s n a r t d n a d e d o c n e b 0 1 / b 8 s i . 2 e l b a t n i d e t a c i d n i s a d e t a r e n e g e r a s e c n e u q e s r e t c a r a h c c n e g kl t ti 7 1 pe h t s e s u a c h g i h c n e g k . c l e n n a h c r o f n o i t a r e n e g r e t c a r a h c - k e l b a t e e s ( . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ c n i d n o a t a d ) . 2 c k l c tl t ti 5 1 ps i l a n g i s s i h t , w o l s i k c o l _ h c n e h w . c k c o l c a t a d t i m s n a r t e h t o t n i c n d d n a , c n e g k , ] 7 : 0 [ c n i d n o a t a d k c o l c o t d e s u . d e r o n g i s i c k l c t , h g i h s i k c o l _ h c n e h w . 9 0 0 2 s 7 d n i d 6 d n i d 5 d n i d 4 d n i d 3 d n i d 2 d n i d 1 d n i d 0 d n i d l t ti 7 1 l 6 1 k 5 1 k 4 1 k 7 1 m 6 1 l 6 1 m 5 1 l n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . d l e n n a h c r o f a t a d t i m s n a r t ) . 1 e l b a t e e s ( . d k l c t r o a k l c t f o e g d e g n i s i r e h t n o d n dl t ti 6 1 j] 7 : 0 [ d n i d n o t n e s e r p a t a d , w o l n e h w . d l e n n a h c r o f t o n _ a t a d l a i c e p s , h g i h n e h w . y l l a i r e s d e t t i m s n a r t d n a d e d o c n e b 0 1 / b 8 s i . 2 e l b a t n i d e t a c i d n i s a d e t a r e n e g e r a s e c n e u q e s r e t c a r a h c d n e g kl t ti 7 1 ke h t s e s u a c h g i h d n e g k . d l e n n a h c r o f n o i t a r e n e g r e t c a r a h c - k e l b a t e e s ( . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ d n i d n o a t a d ) . 2 d k l c tl t ti 4 1 ls i l a n g i s s i h t , w o l s i k c o l _ h c n e h w . d k c o l c a t a d t i m s n a r t e h t o t n i d n d d n a , d n e g k , ] 7 : 0 [ d n i d n o a t a d k c o l c o t d e s u w o l ( d k l c t , h g i h = k c o l _ h c , e d o m k c o l l e n n a h c n i . 9 0 0 2 s e t a t s k c o l l e n n a h c e h t t e s e r o t d e s u s i ) s k c o l c 6 1 t s a e l t a r o f . s o f i f x r d n a e n i h c a m c n y sl t ti4 da e t a r e n e g o t d e s u ) 2 e l b a t e e s ( , h g i h n e h w . r e t c a r a h c c n y s . t x e t r e i l r a e e e s . s r e t a r a h c 5 . 8 2 k f o e c n e u q e s l a i c e p s
22 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c table 11. transmitter output signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a x t n a x t . f f i d l c e p v l o7 1 a 7 1 b . a l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h p b x t n b x t . f f i d l c e p v l o7 1 c 7 1 d . b l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h p c x t n c x t . f f i d l c e p v l o7 1 e 6 1 f . c l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h p d x t n d x t . f f i d l c e p v l o7 1 f 7 1 g . d l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h o k l c tl t to 4 1 jd e d i v o r p s i k c o l c s i h t . e t a r a t a d l e l l a r a p e h t t a k c o l c t u p t u o l t t . y r t i u c r i c m a e r t s - p u y b e s u r o f 2 o k l c tl t to4 gk c o l c s i h t . 2 y b d e d i v i d e t a r a t a d l e l l a r a p e h t t a k c o l c t u p t u o l t t . y r t i u c r i c m a e r t s - p u y b e s u r o f d e d i v o r p s i
23 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c table 12. mode control signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d k c o l _ h cl t ti4 es k c o l h g i h k c o l _ h c . l o r t n o c e d o m t u p n i l e l l a r a p . k c o l l e n n a h c ) . 1 e l b a t e e s ( . r e h t e g o t s l e n n a h c r u o f l l a k l c f e rl t ti 7 1 hk c e h c y c n e u q e r f d n a o c v t i m s n a r t e h t r o f d e s u . k c o l c e c n e r e f e r . a t a d l a i r e s r e v i e c e r e h t m o r f d e r e v o c e r k c o l c e h t r o f n _ t e s e rl t ti 5 1 cs i l l p r e v i e c e r e h t . t e s e r n i d l e h s i 9 0 0 2 s e h t , w o l n e h w . t e s e r g n i s i r e h t n o d e z i l a i t i n i e r a s o f i f e h t . k l c f e r e h t o t k c o l o t d e c r o f . y l l a m r o n s e t a r e p o 9 0 0 2 s e h t , h g i h n e h w . n _ t e s e r f o e g d e e t a rl t ti 2 1 de t a r t u p t u o l a i r e s e h t h t i w s e t a r e p o 9 0 0 2 s e h t , w o l n e h w . e t a r h t i w s e t a r e p o 9 0 0 2 s e h t , h g i h n e h w . y c n e u q e r f o c v e h t o t l a u q e . s n o i t c n u f l l a r o f 2 y b d e d i v i d y l l a n r e t n i o c v e h t n _ a l q sl t ti 4 1 ee r a s t u p t u o l a i r e s e h t , h g i h n e h w . a l e n n a h c r o f l o r t n o c h c l e u q s n w o d d e r e w o p s i r e v i r d t u p t u o r e t t i m s n a r t e h t , w o l n e h w . e v i t c a . e v i t c a n i e m o c e b s t u p t u o e h t d n a n _ b l q sl t ti 6 1 de r a s t u p t u o l a i r e s e h t , h g i h n e h w . b l e n n a h c r o f l o r t n o c h c l e u q s n w o d d e r e w o p s i r e v i r d t u p t u o r e t t i m s n a r t e h t , w o l n e h w . e v i t c a . e v i t c a n i e m o c e b s t u p t u o e h t d n a n _ c l q sl t ti 4 1 fe r a s t u p t u o l a i r e s e h t , h g i h n e h w . c l e n n a h c r o f l o r t n o c h c l e u q s n w o d d e r e w o p s i r e v i r d t u p t u o r e t t i m s n a r t e h t , w o l n e h w . e v i t c a . e v i t c a n i e m o c e b s t u p t u o e h t d n a n _ d l q sl t ti 5 1 fe r a s t u p t u o l a i r e s e h t , h g i h n e h w . d l e n n a h c r o f l o r t n o c h c l e u q s n w o d d e r e w o p s i r e v i r d t u p t u o r e t t i m s n a r t e h t , w o l n e h w . e v i t c a . e v i t c a n i e m o c e b s t u p t u o e h t d n a note: all ttl inputs except refclk have internal pull-up networks.
24 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c table 13. receiver output pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 a t u o d 6 a t u o d 5 a t u o d 4 a t u o d 3 a t u o d 2 a t u o d 1 a t u o d 0 a t u o d l t to1 j 3 j 2 j 1 h 2 h 3 h 1 f 2 g d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r a l e n n a h c g n i s i r n o d i l a v d n a e d o m k c o l c l l u f n i p a c r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i n a c r d n a p a c r h t o b f o e g d e a f o el t to2 fs e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e a l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t ) . 7 e l b a t e e s ( . ] 7 : 0 [ a t u o d s t u p t u o a t a d a g a l f kl t to3 ga t a h t s e t a c i d n i a g a l f k n i h g i h a . g a l f r e t c a r a h c - k a l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ a t u o d e c a f r e t n i l e l l a r a p ) . 7 e l b a t e e s ( . d e v i e c e r s a w r e t c a r a h c a r r el t to1 ge h t s e i f i n g i s a r r e n o h g i h a . r o r r e e v i e c e r a l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o ) . 7 e l b a t e e s ( . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d a l o ll t to5 ce h t t a h t s e t a c i d n i h g i h a l o l . d e t c e t e d k c o l f o s s o l a l e n n a h c n e h w t r e s s a e d l l i w l a n g i s s i h t . k c o l t i b t s o l s a h a l e n n a h c n o u r c s i h t , e d o m k c o l l e n n a h c n i n e h w . a t a d o t d e k c o l s a h u r c e h t t i b t o n s i u r c a l e n n a h c e h t t a h t g n i t a c i d n i t r e s s a l l i w l a n g i s ) . 7 e l b a t e e s ( . y l s u o n o r h c n y s a t r o p e r l l i w s i h t . d e k c o l p a c r n a c r l t to2 k 1 k , a t a d e v i e c e r l e l l a r a p . a l e n n a h c r o f k c o l c a t a d e v i e c e r g n i s i r e h t n o d i l a v e r a a r r e d n a , a g a l f k , a f o e , ] 7 : 0 [ a t u o d e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i n e h w p a c r f o e g d e . e d o m k c o l c f l a h n i n a c r d n a p a c r h t o b f o 7 b t u o d 6 b t u o d 5 b t u o d 4 b t u o d 3 b t u o d 2 b t u o d 1 b t u o d 0 b t u o d l t to1 r 1 p 3 m 2 n 2 m 1 n 2 l 1 m d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r b l e n n a h c g n i s i r n o d i l a v d n a e d o m k c o l c l l u f n i p b c r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i n b c r d n a p b c r h t o b f o e g d e b f o el t to1 ls e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e b l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t ) . 7 e l b a t e e s ( . ] 7 : 0 [ b t u o d s t u p t u o a t a d b g a l f kl t to2 pa t a h t s e t a c i d n i b g a l f k n i h g i h a . g a l f r e t c a r a h c - k b l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ b t u o d e c a f r e t n i l e l l a r a p ) . 7 e l b a t e e s ( . d e v i e c e r s a w r e t c a r a h c
25 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d b r r el t to3 ke h t s e i f i n g i s b r r e n o h g i h a . r o r r e e v i e c e r b l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o ) . 7 e l b a t e e s ( . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d b l o ll t to7 de h t t a h t s e t a c i d n i h g i h b l o l . d e t c e t e d k c o l f o s s o l b l e n n a h c n e h w t r e s s a e d l l i w l a n g i s s i h t . k c o l t i b t s o l s a h b l e n n a h c n o u r c s i h t , e d o m k c o l l e n n a h c n i n e h w . a t a d o t d e k c o l s a h u r c e h t t i b t o n s i u r c b l e n n a h c e h t t a h t g n i t a c i d n i t r e s s a l l i w l a n g i s ) . 7 e l b a t e e s ( . y l s u o n o r h c n y s a t r o p e r l l i w s i h t . d e k c o l p b c r n b c r l t to1 u 1 t , a t a d e v i e c e r l e l l a r a p . b l e n n a h c r o f k c o l c a t a d e v i e c e r g n i s i r e h t n o d i l a v e r a b r r e d n a , b g a l f k , b f o e , ] 7 : 0 [ b t u o d e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i n e h w p b c r f o e g d e . e d o m k c o l c f l a h n i n b c r d n a p b c r h t o b f o 7 c t u o d 6 c t u o d 5 c t u o d 4 c t u o d 3 c t u o d 2 c t u o d 1 c t u o d 0 c t u o d l t to7 r 6 r 5 t 3 u 4 t 5 r 2 u 3 t s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r c l e n n a h c n o d i l a v d n a e d o m k c o l c l l u f n i p c c r f o e g d e g n i s i r e h t n o d i l a v . e d o m k c o l c f l a h n i n c c r d n a p c c r h t o b f o e g d e g n i s i r e h t c f o el t to2 rs e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e c l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t ) . 7 e l b a t e e s ( . ] 7 : 0 [ c t u o d s t u p t u o a t a d c g a l f kl t to3 pa t a h t s e t a c i d n i c g a l f k n i h g i h a . g a l f r e t c a r a h c - k c l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ c t u o d e c a f r e t n i l e l l a r a p ) . 7 e l b a t e e s ( . d e v i e c e r s a w r e t c a r a h c c r r el t to2 te h t s e i f i n g i s c r r e n o h g i h a . r o r r e e v i e c e r c l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o ) . 7 e l b a t e e s ( . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d c l o ll t to9 ce h t t a h t s e t a c i d n i h g i h c l o l . d e t c e t e d k c o l f o s s o l c l e n n a h c n e h w t r e s s a e d l l i w l a n g i s s i h t . k c o l t i b t s o l s a h c l e n n a h c n o u r c s i h t , e d o m k c o l l e n n a h c n i n e h w . a t a d o t d e k c o l s a h u r c e h t t i b t o n s i u r c c l e n n a h c e h t t a h t g n i t a c i d n i t r e s s a l l i w l a n g i s ) . 7 e l b a t e e s ( . y l s u o n o r h c n y s a t r o p e r l l i w s i h t . d e k c o l p c c r n c c r l t to5 u 4 u , a t a d e v i e c e r l e l l a r a p . c l e n n a h c r o f k c o l c a t a d e v i e c e r g n i s i r e h t n o d i l a v e r a c r r e d n a , c g a l f k , c f o e , ] 7 : 0 [ c t u o d e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i n e h w p c c r f o e g d e . e d o m k c o l c f l a h n i n c c r d n a p c c r h t o b f o table 13. receiver output pin assignment and descriptions (continued)
26 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 d t u o d 6 d t u o d 5 d t u o d 4 d t u o d 3 d t u o d 2 d t u o d 1 d t u o d 0 d t u o d l t to 1 1 u 0 1 r 9 u 9 r 9 t 8 u 7 u 8 t d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r d l e n n a h c g n i s i r n o d i l a v d n a e d o m k c o l c l l u f n i p d c r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i n d c r d n a p d c r h t o b f o e g d e d f o el t to6 us e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e d l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t ) . 7 e l b a t e e s ( . ] 7 : 0 [ d t u o d s t u p t u o a t a d d g a l f kl t to7 ta t a h t s e t a c i d n i d g a l f k n i h g i h a . g a l f r e t c a r a h c - k d l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ d t u o d e c a f r e t n i l e l l a r a p ) . 7 e l b a t e e s ( . d e v i e c e r s a w r e t c a r a h c d r r el t to6 te h t s e i f i n g i s d r r e n o h g i h a . r o r r e e v i e c e r d l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o ) . 7 e l b a t e e s ( . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d d l o ll t to 1 1 ce h t t a h t s e t a c i d n i h g i h d l o l . d e t c e t e d k c o l f o s s o l d l e n n a h c n e h w t r e s s a e d l l i w l a n g i s s i h t . k c o l t i b t s o l s a h d l e n n a h c n o u r c s i h t , e d o m k c o l l e n n a h c n i n e h w . a t a d o t d e k c o l s a h u r c e h t t i b t o n s i u r c d l e n n a h c e h t t a h t g n i t a c i d n i t r e s s a l l i w l a n g i s ) . 7 e l b a t e e s ( . y l s u o n o r h c n y s a t r o p e r l l i w s i h t . d e k c o l p d c r n d c r l t to 0 1 t 0 1 u , a t a d e v i e c e r l e l l a r a p . d l e n n a h c r o f k c o l c a t a d e v i e c e r g n i s i r e h t n o d i l a v e r a d r r e d n a , d g a l f k , d f o e , ] 7 : 0 [ d t u o d e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i n e h w p d c r f o e g d e . e d o m k c o l c f l a h n i n d c r d n a p d c r h t o b f o table 13. receiver output pin assignment and descriptions (continued)
27 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c table 14. receiver input pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a x r n a x r . f f i d l c e p v l i2 a 3 a e h t s i p a x r . a l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d v o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n a x r , t u p n i e v i t i s o p d d . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - p b x r n b x r . f f i d l c e p v l i5 a 5 b e h t s i p b x r . b l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d v o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n b x r , t u p n i e v i t i s o p d d . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - p c x r n c x r . f f i d l c e p v l i8 a 9 a e h t s i p c x r . c l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d v o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n c x r , t u p n i e v i t i s o p d d . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - p d x r n d x r . f f i d l c e p v l i1 1 b 2 1 b e h t s i p d x r . d l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d v o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n d x r , t u p n i e v i t i s o p d d . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - table 15. receiver control signals e m a n n i pe m a n n i p e m a n n i p e m a n n i pe m a n n i pl e v e ll e v e l l e v e l l e v e ll e v e lo / io / i o / i o / io / i# n i p# n i p # n i p # n i p# n i pn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d a n e p l b n e p l c n e p l d n e p l l t ti 4 1 d 4 1 g 5 1 g 4 1 h l a i r e s d e e p s h g i h e h t s i e c r u o s t u p n i , w o l n e h w . e l b a n e k c a b p o o l h c a e r o f t u p t u o l a i r e s e h t , h g i h n e h w . l e n n a h c h c a e r o f t u p n i . t u p n i s t i o t k c a b d e p o o l s i l e n n a h c e d o m cl t ti2 cs k c o l c t u p t u o l e l l a r a p e h t , w o l n e h w . l o r t n o c e d o m k c o l c l e l l a r a p e h t , h g i h n e h w . e t a r a t a d e h t 2 / 1 o t l a u q e s i e t a r ) n / p x c r ( n e h w . e t a r a t a d e h t o t l a u q e s i e t a r ) n / p x c r ( s k c o l c t u p t u o s y a w l a l l i w f o e t s a l e h t , ) d e l b a n e g n i h c t e r t s a t a d ( 0 = e d o m c . f o e n o n e r o f e b , p x c r y b d e k c o l c e b note: all ttl inputs except refclk have internal pull-up networks.
28 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c e m a n n i p. y t q# n i pn o i t p i r c s e d a d d v5, 6 a , 1 a 6 1 a , 3 1 a 8 c v ( r e w o p g o l a n a d d . e s i o n w o l ) a s s v5, 8 b , 7 b , 4 c , 5 1 b 1 1 d v ( d n u o r g g o l a n a s s . ) d d v6, 5 1 a , 2 1 a , 6 b , 4 b 9 d , 6 c v ( y r t i u c r i c d e e p s h g i h r o f r e w o p d d . ) s s v5, 1 1 a , 4 a , 4 1 b , 0 1 b 6 d v ( y r t i u c r i c d e e p s h g i h r o f d n u o r g s s . ) b u s s s v5, 4 1 a , 7 a , 5 d , 3 1 c 8 d v ( y r t i u c r i c d e e p s h g i h r o f d n u o r g s s . ) r w p l c e p4, 5 1 e , 5 1 d 6 1 g , 6 1 e v ( r e w o p l c e p d d ) d n g l c e p26 1 c 6 1 h v ( d n u o r g l c e p s s ) r w p g i d6, 2 b , 1 b , 7 1 j , 3 e 9 p , 4 l v ( r e w o p y r t i u c r i c e r o c d d ) d n g g i d8, 3 c , 1 c , 4 f , 2 d , 4 n , 5 1 j 3 r , 0 1 p v ( d n u o r g y r t i u c r i c e r o c s s ) r w p l t t7, 4 h , 1 e , 3 n , 4 k , 7 p , 5 p 8 p v ( o / i l t t r o f r e w o p d d ) d n g l t t0 1, 2 e , 1 d , 4 j , 3 f 4 m , 3 l , 6 p , 4 p 8 r , 4 r v ( o / i l t t r o f d n u o r g s s ) table 16. power and ground signals
29 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d s m tl t ti 0 1 a. e c i v e d f o g n i t s e t g a t j s e l b a n e . t c e l e s e d o m t s e t k c tl t ti 0 1 c. k c o l c t s e t g a t j . k c o l c t s e t i d tl t ti 0 1 d. t u p n i a t a d g a t j . n i a t a d t s e t o d tl t t o e t a t s i r t 5 1 h r e d n u e c n a d e p m i h g i h e b n a c . t u p t u o a t a d g a t j . t u o a t a d t s e t . d n a m m o c r e l l o r t n o c g a t j s r tl t ti3 b. e n i h c a m e t a t s t s e t g a t j s t e s e r . t e s e r t s e t table 17. jtag test signals table 16. power and ground signals (continued) e m a n n i p. y t q# n i pn o i t p i r c s e d r w p3, 6 1 b , 3 1 b 2 1 c r e w o p d n g13 dd n u o r g 1 p a c 2 p a c 23 1 d 4 1 c d e t c e n n o c e r a s r o t s i s e r d n a r o t i c a p a c r e t l i f p o o l l a n r e t x e e h t . s n i p r e t l i f p o o l . s n i p e s e h t o t c n27 c , 9 b. t c e n n o c t o n o d . s n i p t s e t s a d e s u . d e t c e n n o c t o n
30 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c figure 10. S2009 pinout (bottom view) a b c d e f g h j k l m n p r t u 1 a d d vr w p g i dd n g g i dd n g l t tr w p l t t1 a t u o da r r e4 a t u o d7 a t u o dn a c rb f o e0 b t u o d2 b t u o d6 b t u o d7 b t u o dn b c rp b c r 2 p a x rr w p g i de d o m cd n g g i dd n g l t ta f o e0 a t u o d3 a t u o d5 a t u o dp a c r1 b t u o d3 b t u o d4 b t u o db g a l f kc f o ec r r e1 c t u o d 3 n a x rs r td n g g i dd n gr w p g i dd n g l t ta g a l f k2 a t u o d6 a t u o db r r ed n g l t t5 b t u o dr w p l t tc g a l f kd n g g i d0 c t u o d4 c t u o d 4 s s vd d va s s vc n y sk c o l _ h cd n g g i d2 o k l c tr w p l t td n g l t tr w p l t tr w p g i dd n g l t td n g g i dd n g l t td n g l t t3 c t u o dn c c r 5 p b x rn b x ra l o lb u s s s v r w p l t t2 c t u o d5 c t u o dp c c r 6 a d d vd d vd d vs s v d n g l t t6 c t u o dd r r ed f o e 7 b u s s s va s s vc nb l o l r w p l t t7 c t u o dd g a l f k1 d t u o d 8 p c x ra s s va d d vb u s s s v r w p l t td n g l t t0 d t u o d2 d t u o d 9 n c x rc nc l o ld d v r w p g i d4 d t u o d3 d t u o d5 d t u o d 0 1 s m ts s vk c ti d t d n g g i d6 d t u o dp d c rn d c r 1 1 s s vp d x rd l o la s s v 2 a n i d1 a n i d0 a n i d7 d t u o d 2 1 d d vn d x rr w pe t a r 7 a n i d6 a n i d4 a n i da k l c t 3 1 a d d vr w pb u s s s v1 p a c 1 b n i db k l c t5 a n i d3 a n i d 4 1 b u s s s vs s v2 p a ca n e p ln _ a l q sn _ c l q sb n e p ld n e p lo k l c t4 d n i dd k l c t5 c n i d0 c n i d6 b n i d4 b n i d0 b n i da n e g k 5 1 d d va s s vn _ t e s e r l c e p r w p l c e p r w p n _ d l q sc n e p lo d td n g g i d5 d n i d0 d n i d7 c n i d2 c n i dc k l c t7 b n i d5 b n i da n d 6 1 a d d vr w pd n g l c e pn _ b l q s l c e p r w p n c x t l c e p r w p d n g l c e pd n d6 d n i d2 d n i d1 d n i d6 c n i d3 c n i db n db n e g k2 b n i d 7 1 p a x tn a x tp b x tn b x tp c x tp d x tn d x tk l c f e rr w p g i dd n e g k7 d n i d3 d n i dc n dc n e g k4 c n i d1 c n i d3 b n i d note: nc used as test pins. do not connect.
31 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c figure 11. S2009 pinout (top view) u t r p n m l k j h g f e d c b a p b c rn b c r7 b t u o d6 b t u o d2 b t u o d0 b t u o db f o en a c r7 a t u o d4 a t u o da r r e1 a t u o dr w p l t td n g l t td n g g i dr w p g i da d d v 1 1 c t u o dc r r ec f o eb g a l f k4 b t u o d3 b t u o d1 b t u o dp a c r5 a t u o d3 a t u o d0 a t u o da f o ed n g l t td n g g i de d o m cr w p g i dp a x r 2 4 c t u o d0 c t u o dd n g g i dc g a l f kr w p l t t5 b t u o dd n g l t tb r r e6 a t u o d2 a t u o da g a l f kd n g l t tr w p g i dd n gd n g g i ds r tn a x r 3 n c c r3 c t u o dd n g l t td n g l t td n g g i dd n g l t tr w p g i dr w p l t td n g l t tr w p l t t2 o k l c td n g g i dk c o l _ h cc n y sa s s vd d vs s v 4 p c c r5 c t u o d2 c t u o dr w p l t t b u s s s va l o ln b x rp b x r 5 d f o ed r r e6 c t u o dd n g l t t s s vd d vd d va d d v 6 1 d t u o dd g a l f k7 c t u o dr w p l t t b l o lc na s s vb u s s s v 7 2 d t u o d0 d t u o dd n g l t tr w p l t t b u s s s va d d va s s vp c x r 8 5 d t u o d3 d t u o d4 d t u o dr w p g i d d d vc l o lc nn c x r 9 n d c rp d c r6 d t u o dd n g g i d i d tk c ts s vs m t 0 1 7 d t u o d0 a n i d1 a n i d2 a n i d a s s vd l o lp d x rs s v 1 1 a k l c t4 a n i d6 a n i d7 a n i d e t a rr w pn d x rd d v 2 1 3 a n i d5 a n i db k l c t1 b n i d 1 p a cb u s s s vr w pa d d v 3 1 a n e g k0 b n i d4 b n i d6 b n i d0 c n i d5 c n i dd k l c t4 d n i do k l c td n e p lb n e p ln _ c l q sn _ a l q sa n e p l2 p a cs s vb u s s s v 4 1 a n d5 b n i d7 b n i dc k l c t2 c n i d7 c n i d0 d n i d5 d n i dd n g g i do d tc n e p ln _ d l q s l c e p r w p l c e p r w p n _ t e s e ra s s vd d v 5 1 2 b n i db n e g kb n d3 c n i d6 c n i d1 d n i d2 d n i d6 d n i dd n dd n g l c e p l c e p r w p n c x t l c e p r w p n _ b l q sd n g l c e pr w pa d d v 6 1 3 b n i d1 c n i d4 c n i dc n e g kc n d3 d n i d7 d n i dd n e g kr w p g i dk l c f e rn d x tp d x tp c x tn b x tp b x tn a x tp a x t 7 1 note: nc used as test pins. do not connect.
32 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c figure 12. compact 23 mm x 23 mm 208 pin tbga package thermal management e g a k c a p x a m r e w o p w o l f r i a q a j q c j w 4 6 . 4m p f l 0 0 2w / c ? 9 . 2 1w / c ? 0 . 3 note: the S2009 requires an airflow of 200 linear feet per minute (lfpm) for proper thermal management. q ja value corresponds to a 200 lfpm environment.
33 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c tclkx, tclka dinx[0:7], dnx, kgenx, sync t 1 t 2 serial data out figure 13. transmitter timing (independent or channel lock mode) table 18. S2009 transmitter timing (independent or channel lock mode) 1. all ac measurements are made from the reference voltage levels of the clock (1.4 v) to the valid input or output data levels (0.8 v or 2.0 v). r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 k l c t . t . r . w p u t e s a t a d0 5 7-s p. 1 e t o n e e s t 2 k l c t . t . r . w d l o h a t a d5 2 3-s p d n a x k l c t n e e w t e b t f i r d e s a h p k l c f e r 3 -3 +s n r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c t t r e t t i j r e t t i j o k l c t e g d e o t e g d e0 3 1s p. k a e p o t k a e p t r t , f s e m i t l l a f d n a e s i r o k l c t4 . 1s n . 2 e t o n e e s . 9 1 e r u g i f e e s t 2 t r e t t i j r e t t i j 2 o k l c t e g d e o t e g d e6 5 1s p. k a e p o t k a e p t r t , f s e m i t l l a f d n a e s i r 2 o k l c t5 . 1s n . 2 e t o n e e s . 9 1 e r u g i f e e s t 2 c to tc t w e k s o k l c t o t 2 o k l c t18 . 2s n s d a e l 2 o k l c t e g d e g n i s i r , o k l c t . e g d e g n i s i r o t e t a r w e l se t a r w e l s t u p n i2s n. 1 e t o n e e s e l c y c y t u de l c y c y t u d 2 o k l c t , o k l c t0 40 6% . 1 e t o n e e s e l c y c y t u de l c y c y t u d t u p n i x k l c t5 35 6% . 1 e t o n e e s table 19. S2009 tclko, tclko2, and tclkx performance specifications 1. unless otherwise specified, all ac measurements are made from the reference voltage levels of the clock (1.4 v) to the valid input or output data levels (0.8 v or 2.0 v). 2. ttl/cmos ac timing measurements are assumed to have an output load of 10 pf.
34 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c table 20. S2009 receiver timing (full and half clock mode) 1. measurements made from the reference voltage levels of the clock (1.4 v) to the valid input or output data levels (0.8 v or 2.0 v). 2. ttl/cmos ac timing measurements are assumed to have an output load of 10 pf. r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 3 n / p x c r . t . r . w p u t e s a t a d 5 . 2 5 . 1 s n s n s p b g 3 . 1 s p b g 2 5 5 5 . 1 t 4 n / p x c r . t . r . w d l o h a t a d5 . 1s n t 5 n / p x c r . t . r . w p u t e s a t a d 5 . 2 0 . 1 s n s p b g 3 . 1 t a s p b g 2 5 5 5 . 1 t a 2 , 1 t 6 n / p x c r . t . r . w d l o h a t a d0 . 1s n t 7 o t e s i r p x c r m o r f e m i t e s i r n x c r 5 . 7 8 . 5 5 . 8 8 . 7 s n s n s p b g 3 . 1 t a s p b g 2 5 5 5 . 1 t a 2 , 1 t p r t , p f s e m i t l l a f d n a e s i r p x c r0 0 9s p. 9 1 e r u g i f e e s . 2 e t o n e e s t n r t , n f s e m i t l l a f d n a e s i r n x c r0 0 9s p. 9 1 e r u g i f e e s . 2 e t o n e e s t r d t , f d s e m i t l l a f d n a e s i r x t u o d4 . 2s n. 9 1 e r u g i f e e s . 2 e t o n e e s e l c y c y t u de l c y c y t u d n / p x c r0 40 6% . 1 e t o n e e s
35 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c figure 15. receiver timing (half clock mode, cmode = 0) figure 14. receiver timing (full clock mode, cmode = 1) rcxn doutx[0:7], eofx, kflagx, errx serial data in t 3 t 4 rcxp rcxn doutx[0:7], eofx, kflagx, errx serial data in rcxp t 5 t 6 t 7 t 5 t 6
36 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g o t t c e p s e r h t i w d d v n o e g a t l o v5 . 0 -1 . 5 +v n i p t u p n i l t t y n a n o e g a t l o v5 . 0 -7 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v0v d d v t n e r r u c k n i s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l c e p d e e p s h g i h5 2a m y t i v i t i s n e s d s e 1 ) s n i p l l a (v 0 0 2 r e v o r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a00 7c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 3 1c ? o t t c e p s e r h t i w n i p r e w o p y n a n o e g a t l o v v / d n g s s 3 1 . 33 . 37 4 . 3v n i p t u p n i l t t y n a n o e g a t l o v07 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o vv d d 2 -v d d v r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t fe c n a r e l o t y c n e u q e r f0 0 1 -0 0 1 +m p p | 0 2 / e t a r a t a d C y c n e u q e r f k l c f e r | 0 0 2 < d t 2 - 1 y r t e m m y s0 40 6% . t p % 0 5 t a e l c y c y t u d t r c r t , f c r e m i t l l a f d n a e s i r k l c f e r2s n. % 0 8 - % 0 2 r e t t i j0 8s p n i a t n i a m o t , k a e p - o t - k a e p 3 . g n i n e p o e y e % 7 7 table 21. absolute maximum ratings table 22. recommended operating conditions table 23. reference clock requirements 1. human body model.
37 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v h o ) l t t ( e g a t l o v h g i h t u p t u o4 . 28 . 2v d d vi x a m h o i p y t , a m 8 = h o a m 2 1 = v l o ) l t t ( e g a t l o v w o l t u p t u od n g5 2 0 . 05 . 0v i n i m l o i p y t , a m 8 C = l o a m 2 1 C = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2v v l i ) l t t ( e g a t l o v w o l t u p n id n g8 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 4a v n i v , v 4 . 2 = d d x a m = i l i ) l t t ( t n e r r u c w o l t u p n i0 0 6a v n i v , v 8 . 0 = d d x a m = i d d t n e r r u c y l p p u s0 0 80 9 9a m. n r e t t a p 0 1 0 1 p d n o i t a p i s s i d r e w o p5 6 . 25 . 3w . n r e t t a p 0 1 0 1 c n i e c n a t i c a p a c t u p n i3f p table 26. dc characteristics r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c r e t t i j l a t o tr e t t i j l a t o t t u p t u o a t a d l a i r e s5 4 1s p. k a e p - o t - k a e p t j d r e t t i j c i t s i n i m r e t e d t u p t u o a t a d l a i r e s6 10 4s p. k a e p - o t - k a e p t r s t , f s e m i t l l a f d n a e s i r t u p t u o a t a d l a i r e s5 7 2s p. % 0 8 - % 0 2 r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c t k c o l ) y c n e u q e r f ( e m i t k c o l n o i t i s i u q c a y c n e u q e r f ) s p b g 2 5 5 5 . 1 ( ) k c o l f o s s o l ( 5 7 1s e l p m a s n r e t t a p e l d i b 0 1 / b 8 . p u t r a t s e c i v e d m o r f , s i s a b t k c o l ) e s a h p ( e s a h p ( e m i t k c o l n o i t i s i u q c a e s a h p ) s p b g 2 5 5 5 . 1 ( ) y t i u n i t n o c s i d 0 5 1s n e e s ( e y e a t a d t u p n i % 0 9 . ) 3 2 e r u g i f 0 8 1s n. e y e a t a d t u p n i % 0 7 t j d e c n a r e l o t r e t t i j t u p n i c i t s i n i m r e t e d0 8 2s p r e t t i j t u p n i e c n a r e l o t r e t t i j l a t o t t u p n i a t a d l a i r e s e c n a r e l o t 2 6 4s p r r s r , f s e m i t l l a f d n a e s i r t u p n i a t a d l a i r e s0 3 3s p. % 0 8 - % 0 2 table 24. serial data timing, transmit outputs 1 table 25. serial data timing, receive inputs 1. output loading is 100 w line-to-line.
38 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c v in (+) v in (? v in (+) ?v in (? v swing v id = 2 x v swing v cm = v in (+) + v in (-) 2 l o b m y sn i mp y tx a ms t i n us n o i t i d n o c v d i 1 0 0 10 0 40 0 6 2v m. 1 2 e r u g i f d n a 6 1 e r u g i f e e s v m c 2 v d d 3 . 1 Cv. 6 1 e r u g i f e e s figure 16. differential input voltage (note: v in (+) C v in (-) is the algebraic difference of the input signals.) table 27. differential lvpecl characteristics 1. differential input voltage. 2. common mode range.
39 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c v out (+) v out (? v out (+) ?v out (? v swing v od = 2 x v swing v cm = v out (+) + v out (-) 2 l o b m y sn i mp y tx a ms t i n us n o i t i d n o c v d o 1 0 0 4 10 0 6 10 0 6 2v m. 0 2 e r u g i f d n a 7 1 e r u g i f e e s v m c 2 v d d 3 . 2 Cv. 7 1 e r u g i f e e s figure 17. differential output voltage table 28. differential lvpecl characteristics (note: v out (+) C v out (-) is the algebraic difference of the input signals.) 1. differential output voltage. 2. common mode range.
40 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c output load the S2009 serial outputs do not require output pulldown resistors. acquisition time with the input eye diagram shown in figure 23, the S2009 will recover data with a 1e-9 ber within the time specified by t lock in table 25 after an instanta- neous phase shift of the incoming data. figure 21. high speed differential inputs figure 18. serial input/output rise and fall time figure 22. receiver input eye diagram jitter mask figure 19. ttl input/output rise and fall time figure 20. serial output load figure 23. acquisition time eye diagram t r t f 80% 20% 50% 80% 20% 50% t r t f +2.0 v +0.8 v +2.0 v +0.8 v 0.01 f 0.01 f v dd -2.3 v 100 0.01 f 0.01 f v dd -1.3 v bit time amplitude 24% 1.3 normalized amplitude normalized time 1.0 0.0 0.2 0.3 0.5 0.7 0.8 0.1 0.6 0.4 0.3 0.7 0.9 1.0 0.0 0.05 0.95
41 S2009 1.6 gbps quad serial backplane device february 9, 2001 / revision c figure 24. loop filter capacitor connections cap1 270 22 nf cap2 270 S2009
42 1.6 gbps quad serial backplane device S2009 february 9, 2001 / revision c amcc is a registered trademark of applied micro circuits corporation. copyright ? 2000 applied micro circuits corporation d59/r438 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 ordering information x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i - s9 0 0 2a g b t 8 0 2 C b t x xxxx xx prefix device package

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